This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-124405, filed Apr. 30, 1999, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, particularly, to an improvement of a gate electrode for an N-type MIS transistor and a P-type MIS transistor.
2. Description of the Related Art
For improving the performance of the MIS transistor, it is absolutely necessary to make the device finer. However, a silicon oxide film used nowadays as a gate insulating film is low in its dielectric constant, giving rise to the problem that it is impossible to increase the capacitance of the gate insulating film. Also, a polycrystalline silicon (polysilicon) used as a gate electrode has a high resistivity, resulting in failure to lower the resistance. To overcome these problems, it is proposed to use a film having a high dielectric constant for forming the gate insulating film to use a metallic material for forming the gate electrode.
However, these materials are poor in heat resistance, compared with the materials used nowadays. Under the circumstances, proposed is a damascene gate technology that permits forming a gate insulating film and a gate electrode after a high temperature process.
In the damascene gate technology, a dummy gate is formed in advance in a region where a gate is to be formed later. The dummy gate is removed after formation of the source-drain diffusion layers, and an electrode material is buried in the region from which the dummy gate has been removed so as to form a gate electrode.
If the same material is used for forming the gate electrodes of the N-type and P-type MIS transistors in the case of forming the gate electrode by employing the damascene gate technology, it is impossible to make the gate electrodes of these transistors differ from each in the work function. As a result, it is impossible to make appropriate the threshold voltage of each of the N-type and P-type MIS transistors. Therefore, a manufacturing process using different gate electrode materials is required for manufacturing an N-type MIS transistor and a P-type MIS transistor. FIGS. 15A to 15I collectively exemplify such a manufacturing process.
In the first step, an element isolating region 502 of an STI structure is formed on a silicon substrate 501, as shown in FIG. 15A. Then, a silicon oxide film 503 is formed in a thickness of about 6 nm as a dummy insulating film that is to be removed later. Further, a laminate structure consisting of a polysilicon film 504 having a thickness of about 150 nm and a silicon nitride film 505 having a thickness of about 50 nm is formed as a dummy gate that is to be removed later. These dummy insulating film and dummy gate are formed by the ordinary technology such as a film-forming technology including an oxidation, CVD and the like, lithography technology, and RIE technology. After formation of the dummy gate, impurity ions are implanted by using the dummy gate (the polysilicon film 504 and the silicon nitride film 505) as a mask to form a diffusion layer for extension for forming source-drain diffusion layers 506. Then, a gate side wall insulating film consisting of a silicon nitride film 507 having a width of about 40 nm is formed by the CVD technology and the RIE technology, as shown in FIG. 15A.
In the next step, impurity ions are implanted by using the dummy gate (the polysilicon film 504 and the silicon nitride film 505) and the gate side wall insulating film (silicon nitride film 507) as a mask to form impurity diffusion layers having a high impurity concentration, said impurity diffusion layers constituting source-drain diffusion layers 508. Then, a silicide film 509 having a thickness of about 40 nm (cobalt silicide film or a titanium silicide film) is formed in only the source-drain regions by the salicide process technology, as shown in FIG. 15B.
In the next step, an interlayer insulating film 510 is formed, for example, a silicon oxide film by a CVD method. Then, the interlayer insulating film 510 is flattened by a CMP technology so as to expose the surfaces of the silicon nitride films 505 and 507, as shown in FIG. 15C.
Further, the silicon nitride film 505 in an upper portion of the dummy gate is selectively removed by using a phosphoric acid relative to the interlayer insulating film 510. In this step, the silicon nitride film 507 is also etched to the height of the polysilicon film 504. Then, the polysilicon film 504 is selectively removed by the etching technology using radicals of halogen atoms such as fluorine atoms, as shown in FIG. 15D.
In the next step, a groove is formed by removing the dummy silicon oxide film 503 by a wet etching using, for example, hydrofluoric acid, followed by forming a Ta2O5 film 512, which is a high dielectric constant film, as a gate insulating film by, for example, a CVD method. Further, an aluminum film 513, is deposited to form a gate electrode, as shown in FIG. 15E. After formation of the aluminum film 513, the Ta2O5 film 512 and the aluminum film 513 are flattened until the interlayer insulating film 510 is exposed to the surface, as shown in FIG. 15F.
The steps shown in FIGS. 15A to 15F are applied to both the N-type MIS transistor forming region and the P-type MIS transistor forming region, though only one region is shown in the drawings. In the subsequent steps, however, both the N-type MIS transistor (N-type MISFET) forming region and the P-type MIS transistor (P-type MISFET) forming regions are shown in the drawings.
After the step shown in FIG. 15F, the entire surface except the P-type MIS transistor forming region is covered with a resist layer 514 by using a lithography technology, as shown in FIG. 15G. Then, the aluminum film 513 in only the P-type region is removed by the wet etching using a phosphoric acid. In this step, the silicon nitride film 507, which is exposed to the surface, is scarcely etched with phosphoric acid under room temperature, as shown in FIG. 15H.
In the next step, the resist layer 514 is removed and a metal having a work function of about 5 eV, e.g., a cobalt film 515, is deposited on the entire surface, as shown in FIG. 15I. Finally, the cobalt film 515 is flattened by a CMP technology until the interlayer insulating film 510 is exposed to the surface, as shown in FIG. 15J.
In the semiconductor device manufactured by the process described above, the aluminum film 513 forms the gate electrode of the N-type MIS transistor, and the cobalt film 515 forms the gate electrode of the P-type MIS transistor so as to provide a C-MIS transistor. It should be noted that the aluminum film 513 has a work function of about 4.2 eV and the cobalt film 515 has a work function of about 5 eV. It follows that it is possible to make appropriate the work function of the gate electrode in each of the N-type MIS transistor and the P-type MIS transistor. As a result, it is possible to make appropriate the threshold voltage of each of the N-type and P-type MIS transistors.
However, the conventional technology described above gives rise to a serious problem in terms of miniaturization of the device. The particular problem will now be described.
FIGS. 16A, 16B and 16C are plan views schematically showing the constructions in the main portions of FIGS. 15G, 15H and 15J, respectively. The distance between the source-drain regions of the N-type MIS transistor and the source-drain regions of the P-type MIS transistor, i.e., the distance between the devices, is set at D.
If the aluminum film 513 in the P-type region is subjected to a wet etching using the resist layer 514 as a mask in the step shown in FIG. 15H, the wet etching proceeds isotropically. Thus, the etching proceeds deep into the region masked by the resist layer 514. As a result, the aluminum film 513 is etched into the N-type region, as shown in FIG. 16B. Therefore, the manufactured transistor is constructed as show n in FIG. 16C. What should be noted is that, in the N-type region, the gate electrode is formed of the aluminum film and the cobalt film differing from each other in the work function. In other words, regions having different threshold voltages are included in the N-type MIS transistor, making it impossible to set the threshold voltage at a low level.
The above-noted problem will now be studied more in detail. Specifically, the etching amount E in the lateral direction shown in FIG. 16B, which is performed by the wet etching, is larger than the height H of the aluminum film, as shown in FIG. 15H. To be more specific, the height H of the aluminum film is about 150 nm. Therefore, the etching amount E in the lateral direction is larger than 150 nm. It follows that, in order to avoid the difficulty, it is necessary to set the distance D between the devices at a value not smaller than twice the etching amount E in the lateral direction, i.e., not smaller than 300 nm, making it very difficult to miniaturize the device. The miniaturization can be achieved to some extent by decreasing the height H of the aluminum film. However, the gate resistance is increased, if the height H of the aluminum film is decreased. Naturally, the decrease in the height H of the aluminum film fails to provide a satisfactory resolution of the problem.
The conventional technique descried above also gives rise to a serious problem in terms of the reliability of, for example, the gate insulating film. This problem will now be described more in detail.
In the prior art describe above, the aluminum film 513 in the P-type region is removed by the wet etching in the step show in FIG. 15H, followed by forming the cobalt film 515 in the aluminum film-removed region in the steps shown in FIGS. 15I and 15J. Therefore, the surface of the gate insulating film 512 is deteriorated by the etching or the like of the aluminum film 513 so as to give bad influences to the reliability of the gate insulating film.
As described above, in the conventional damascene technology, the lateral etching proceeds prominently in the step of etching the dummy gate, making it difficult to achieve miniaturization of the semiconductor device. Also, the reliability of the gate insulating film or the like is adversely affected by the step of etching the dummy gate.
A first object of the present invention is to achieve miniaturization of a semiconductor device in which the gate electrode is formed by using a damascene gate technology or the like.
A second object of the present invention is to ensure reliability of the gate insulating film and the like.
According to a first aspect of the present invention, there is provided a semiconductor device A having an N-type MIS transistor formed in a first region and a P-type MIS transistor formed in a second region,
wherein, said N-type MIS transistor includes a first gate insulating film formed on at least the bottom of a first concave portion formed in the first region and a first gate electrode formed on said first gate insulating film;
said P-type MIS transistor includes a second gate insulating film formed on at least the bottom of a second concave portion formed in the second region and a second gate electrode formed on said second gate insulating film;
each of said first and second gate electrodes includes at least one metal-containing film, and at least one of the first and second gate electrodes is of a laminate structure including a plurality of the metal-containing films; and
the work function W1 of the metal-containing film constituting at least a part of said first gate electrode and in contact with said first gate insulating film is smaller than the work function W2 of the metal-containing film constituting at least a part of said second gate electrode and in contact with said second gate insulating film.
In the semiconductor device A according to the first aspect of the present invention, it is desirable for the metal-containing film constituting at least a part of the first gate electrode to be selected from a metal film and a metal compound film and for the metal-containing film constituting at least a part of the second gate electrode to be selected from a metal film and a metal compound film. It is desirable for the metal compound film to be selected from a metal silicide film and a metal nitride film. In this case, it is possible for the metal nitride film to contain at least 1% of oxygen.
In the semiconductor device A according to the first aspect of the present invention, it is desirable for the metal-containing film constituting at least a part of the first gate electrode and in contact with the first gate insulating film to be formed along the bottom and the side wall of the first concave portion.
In the semiconductor device A according to the first aspect of the present invention, it is desirable for the metal-containing film constituting at least a part of the second gate electrode and in contact with the second gate insulating film to be formed along the bottom and side wall of the second concave portion.
In the semiconductor device A according to the first aspect of the present invention, it is desirable for the metal-containing film constituting at least a part of the first gate electrode and in contact with the first gate insulating film to have a thickness on a bottom of the first concave portion larger than the thickness on a side wall of the first concave portion.
In the semiconductor device A according to the first aspect of the present invention, it is desirable for the metal-containing film constituting at least a part of the second gate electrode and in contact with the second gate insulating film to have a thickness on a bottom of the second concave portion larger than the thickness on a side wall of the second concave portion.
Further, in the semiconductor device A according to the first aspect of the present invention, it is desirable for the first gate electrode to be formed of a laminate structure consisting of a hafnium nitride film and a cobalt film, for the second gate electrode to be formed of a cobalt film, and for each of said first and second gate insulating films to be formed of a hafnium oxide film.
According to a second aspect of the present invention, there is provided a method B of manufacturing a semiconductor device having an N-type MIS transistor formed in a first region and a P-type MIS transistor formed in a second region, comprising:
forming a first metal-containing film on a first gate insulating film formed on at least the bottom of a first concave portion arranged in said first region and on a second gate insulating film formed on at least the bottom of a second concave portion arranged in said second region;
removing the first metal-containing film formed on one of the first and second gate insulating films;
forming a second metal-containing film on the first metal-containing film remaining on the other of the first and second gate insulating films and on the exposed surface of said one of the first and second gate insulating films;
wherein the work function of one of the first and second metal-containing films constituting at least a part of a first gate electrode of the N-type MIS transistor and in contact with the first gate insulating film is smaller than the work function of the other of the first and second metal-containing films constituting at least a part of a second gate electrode of the P-type MIS transistor and in contact with the second gate insulating film.
According to a third aspect of the present invention, there is provided a method C of manufacturing a semiconductor device having an N-type MIS transistor formed in a first region and a P-type MIS transistor formed in a second region, comprising:
forming a first metal-containing film on a first gate insulating film formed on at least the bottom of a first concave portion arranged in said first region and on a second gate insulating film formed on at least the bottom of a second concave portion arranged in said second region;
removing the first metal-containing film formed on one of the first and second gate insulating films;
forming a third metal-containing film on the first metal-containing film remaining on the other of the first and second gate insulating films and on the exposed surface of said one of the first and second gate insulating films;
removing the third metal-containing film formed on said the other of the first and second gate insulating films; and
forming a second metal-containing film on the third metal-containing film remaining on said one of the first and second gate insulating films and on the exposed surface of the first metal-containing film formed on said the other of the first and second gate insulating films;
wherein the work function of one of the first and third metal-containing films constituting at least a part of a first gate electrode of the N-type MIS transistor and in contact with the first gate insulating film is smaller than the work function of the other of the first and third metal-containing films constituting at least a part of a second gate electrode of the P-type MIS transistor and in contact with the second gate insulating film.
According to the semiconductor device A and the manufacturing methods B and C of the semiconductor device of the present invention, the work function of the metal-containing film in contact with the gate insulating film of the N-type MIS transistor is smaller than the work function of the metal-containing film in contact with the gate insulating film of the P-type MIS transistor. As a result, the work functions of the gate electrodes of the N-type and P-type MIS transistors can be made optimum so as to make optimum the threshold voltages of the N-type and P-type MIS transistors.
Also, according to the semiconductor device A and the manufacturing methods B and C of the semiconductor device of the present invention, the gate electrode of at least one of the N-type MIS transistor and the P-type MIS transistor consists of a laminate structure including a plurality of metal-containing films. As a result, the entire resistance of the gate electrode can be lowered, even if the metal-containing film in contact with the gate insulating film has a high resistivity, by arranging metal-containing films having a low resistivity to form upper layers of the laminate structure.
Further, according to the manufacturing methods B and C of the semiconductor device of the present invention, the second metal-containing film is formed on the first and third metal-containing films, making it possible to decrease the thickness of each of the first and third metal-containing films. Therefore, when the metal-containing film (first or third metal-containing film) formed in one of the first and second gate forming regions is removed, it is possible to prevent the etching from proceeding deep into the other region of the first and second gate forming regions. As a result, the semiconductor device can be miniaturized.
Incidentally, in the semiconductor device A and the manufacturing methods B and C of the semiconductor device of the present invention, it is not absolutely necessary for the materials of the metal-containing films in contact with the gate insulating films of the N-type MIS transistor and the P-type MIS transistor to be different from each other. Even if these metal-containing films are formed of the same materials, it suffices for these metal-containing films to be different from each other in composition or crystal structure as far as these films differ from each other in the work function.
According to a fourth aspect of the present invention, there is provided a method D of manufacturing a semiconductor device having an N-type MIS transistor formed in a first region and a P-type MIS transistor formed in a second region, comprising:
forming a first metal-containing film on a first gate insulating film formed on at least the bottom of a first concave portion arranged in the first region and on a second gate insulating film formed on at least the bottom of a second concave portion arranged in the second region; and
allowing the first metal-containing film formed on one of the first and second gate insulating films to react with a substance other than the substances contained in the first metal-containing film so as to convert the first metal-containing film into a second metal-containing film;
wherein the work function of one of the first and second metal-containing films constituting at least a part of a first gate electrode of the N-type MIS transistor and in contact with the first gate insulating film, is smaller than the work function of the other of the first and second metal-containing films constituting at least a part of a second gate electrode of the P-type MIS transistor and in contact with the second gate insulating film.
According to a fifth aspect of the present invention, there is provided a method E of manufacturing a semiconductor device having an N-type MIS transistor formed in a first region and a P-type MIS transistor formed in a second region, comprising:
forming a first metal-containing film on a first gate insulating film formed on at least the bottom of a first concave portion arranged in the first region and on a second gate insulating film formed on at least the bottom of a second concave portion arranged in the second region;
allowing the first metal-containing film formed on one of the first and second gate insulating films to react with a first substance other than the substances contained in the first metal-containing film so as to convert the first metal-containing film into a second metal-containing film; and
allowing the first metal-containing film formed on the other of the first and second gate insulating films to react with a second substance other than the substances contained in the first metal-containing film so as to convert the first metal-containing film into a third metal-containing film;
wherein the work function of one of the second and third metal-containing films constituting at least a part of a first gate electrode of the N-type MIS transistor and in contact with the first gate insulating film, is smaller than the work function of the other of the second and third metal-containing films constituting at least a part of a second gate electrode of the P-type MIS transistor and in contact with the second gate insulating film.
According to a sixth aspect of the present invention, there is provided a method F of manufacturing a semiconductor device having an N-type MIS transistor formed in a first region and a P-type MIS transistor formed in a second region, comprising:
forming a first metal-containing film on a first gate insulating film formed on at least the bottom of a first concave portion arranged in the first region and on a second gate insulating film formed on at least the bottom of a second concave portion arranged in the second region; and
diffusing a first substance other than the substances contained in the first metal-containing film through the first metal-containing film formed on one of the first and second gate insulating films so as to permit the diffused first substance to be precipitated on the surface of said one of the first and second gate insulating films, thereby forming a second metal-containing film consisting of the first substance on said one of the first and second gate insulating films;
wherein the work function of one of the first and second metal-containing films constituting at least a part of a first gate electrode of the N-type MIS transistor and in contact with the first gate insulating film is smaller than the work function of the other of the first and second metal-containing films constituting at least a part of a second gate electrode of the P-type MIS transistor and in contact with the second gate insulating film.
According to a seventh aspect of the present invention, there is provided a method G of manufacturing a semiconductor device having an N-type MIS transistor formed in a first region and a P-type MIS transistor formed in a second region, comprising:
forming a first metal-containing film on a first gate insulating film formed on at least the bottom of a first concave portion arranged in the first region and on a second gate insulating film formed on at least the bottom of a second concave portion arranged in the second region;
diffusing a first substance other than the substances contained in the first metal-containing film through the first metal-containing film formed on one of the first and second gate insulating films so as to permit the diffused first substance to be precipitated on the surface of said one of the first and second gate insulating films, thereby forming a second metal-containing film consisting of the first substance on said one of the first and second gate insulating films; and
diffusing a second substance other than the substances contained in the first metal-containing film through the first metal-containing film formed on the other of the first and second gate insulating films so as to permit the diffused second substance to be precipitated on said the other of the first and second gate insulating films, thereby forming a third metal-containing film consisting of the second substance on said the other of the first and second gate insulating films;
wherein the work function of one of the second and third metal-containing films constituting at least a part of a first gate electrode of the N-type MIS transistor and in contact with the first gate insulating film, is smaller than the work function of the other of the second and third metal-containing films constituting at least a part of a second gate electrode of the P-type MIS transistor and in contact with the second gate insulating film.
According to the methods D to G of the present invention for manufacturing the semiconductor device, the work function of the metal-containing film in contact with the gate insulating film of the N-type MIS transistor is smaller than the work function of the metal-containing film in contact with the gate insulating film of the P-type MIS transistor. As a result, it is possible to make optimum the work functions of the gate electrodes of the N-type and P-type MIS transistors. It follows that the threshold voltages of the N-type and P-type MIS transistors can be made optimum.
Also, according to the methods D to G of the present invention for manufacturing the semiconductor device, the gate electrode can be formed without etching the metal-containing film formed on the gate insulating film so as to prevent the reliability of the gate insulating film from being lowered.
Incidentally, in the semiconductor device A and the manufacturing methods B to G of the semiconductor device of the present invention, it is desirable for the work function W1 (in the case of the N-type MIS transistor) to be positioned on the side of the conduction band relative to the center of the band gap (xc2xd position of the band gap) of the semiconductor constituting the semiconductor substrate. It is also desirable for the work function W2 (in the case of the P-type MIS transistor) to be positioned on the side of the valence band relative to the center of the band gap. Also, it suffices for the thickness of that region of the metal-containing film which is in contact with the gate insulating film, said thickness determining the threshold voltage of the MIS transistor, to be not smaller than the thickness at which a desired threshold voltage can be obtained. Preferably, the thickness of the metal-containing film in question should be equal to at least the thickness of a layer consisting of about 10 atoms arranged in the thickness direction of the film.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.